Non-volatile memory cells are frequently used to store special bits of an integrated circuit, such as configuration bits, status bits, redundant program bits (memory redundancy programming), protection bits of a memory array, etc. These special bits are generally arranged in a non-volatile register. The content of the register is read in priority by a specific read circuit. The content is transferred into a dynamic register as soon as the supply voltage is applied to the integrated circuit, or before the performance of the first operation by the integrated circuit. For example, the first operation may be a response to a Start command applied to the integrated circuit.
A non-volatile register comprises one or more non-volatile memory elements. Each memory element enables a special bit to be stored. A specific read circuit is associated with each memory element so that the bit stored in the memory can be read to be transferred into the dynamic register. A differential read is generally provided to reduce the non-volatile register read time.
FIG. 1 represents an example embodiment of a memory element NVME1 of a non-volatile register, as well as an example embodiment of a circuit SA1 for reading the memory element. The memory element NVME1 is a differential type and comprises two memory points M11, M12. Each memory point M11, M12 comprises a selection input E0, a gate control input E1, a program input E2, a read input E3 and a source node SLC.
The read circuit SA1 comprises, for example, two inverter gates I1, I2 supplied by a voltage Vcc, which is generally the supply voltage of the integrated circuit in which the assembly is arranged. The gates I1, I2 are head-to-tail connected and form an inverter latch or flip-flop. The input of the gate I1 is linked to the read input E3 of the memory point M11 through a cascode transistor TN1. The input of the gate I2 is linked to the read input E3 of the memory point M12 through a cascode transistor TN2. The output OUT of the read circuit SA1 is taken off at the output of one of the gates I1, I2. In this case, the output is the output of the gate I1.
The memory points M11, M12 are generally configured before the integrated circuit is marketed. Such as, for example, during the test phase prior to marketing the integrated circuit. This configuration involves putting the memory points M11, M12 into complementary states. One memory point is erased and the other memory point is programmed, or vice-versa, depending on the data to be saved in the memory element NVME1.
If the memory point M11 is programmed and the memory point M12 is erased, the memory point M11 is electrically conductive between its read input E3 and the node SLC, while the memory point M12 is not conductive. Thus, when the voltage Vcc appears, the input of the inverter gate I1 (output of the gate I2) is pulled to 0 (ground) and the output OUT changes to 1 (Vcc).
Conversely, if the memory point M12 is programmed and the memory point M11 is erased, the input of the inverter gate I2 (output of the gate I1) is pulled to 0 (ground) and the output OUT changes to 0 when the voltage Vcc appears.
FIG. 2 represents a memory point M1 structure that can be used to produce each of the memory points M11, M12. The memory point Ml comprises a first floating-gate transistor FGT1 for erasing and programming the memory point, and at least a second floating-gate transistor FGT2 for reading the memory point. Each floating-gate transistor is equipped with a selection transistor such that the memory point comprises two selection transistors ST1, ST2. Each floating-gate transistor and its selection transistor form an EEPROM memory cell, respectively C1, C2.
The floating-gate transistors FGT1, FGT2 have their control gates connected to the gate control input E1. The selection transistors ST1, ST2 have their gates connected to the selection input E0. The drain of the transistor FGT1 is linked to the program input E2 through the selection transistor ST1, while its source is linked to the node SLC. The drain of the transistor FGT2 is linked to the read input E3 through the selection transistor ST2, while its source is linked to the node SLC. The node SLC is generally a source line SL.
The floating gates of the transistors FGT1, FGT2 are inter-connected and each comprise a tunnel window TW. The tunnel window corresponds to a region in which the oxide layer between the floating gate and the silicon substrate is very thin (a few atomic layers) so as to enable the removal or injection of charges into the floating gate by the tunnel effect (Fowler Nordheim effect).
The operations of erasing and programming the memory point M1 involve removing or injecting electrical charges into the floating gates of the transistors FGT1, FGT2 by the tunnel effect. This removal or injection is applied to the transistor FGT1 only, through the inputs E0, E1, E2. For this purpose, a high voltage Vpp on the order of 8 to 15 V (depending on the field of technology) is applied to the transistor FGT1 according to an erase or program method to be chosen from the various methods known to those skilled in the art. Since the transistor FGT2 has its floating gate connected to the floating gate of the transistor FGT1, the removal or the injection of electrical charges into the floating gate of the transistor FGT1 is transmitted to the floating gate of the transistor FGT2.
The memory point M1 is read by the transistor FGT2. A read voltage Vread is applied to the control gate of the transistor FGT2 through the input E1. This voltage is, for example, equal to 0 (ground), since a programmed transistor generally has a negative threshold voltage and an erased transistor has a positive threshold voltage. Simultaneously, the voltage Vcc is applied to the selection input E0 so that the selection transistor ST2 is on.
The cascode transistors TN1, TN2 (FIG. 1) receive a bias voltage Vcasc equal to VD+Vt at their gate, with Vt being the threshold voltage of the transistors TN1, TN2. Thus, the voltage received by the drain of the transistor FGT2 during the reading of the memory point is equal to VD. The voltage VD is controlled due to the cascode transistors to avoid the transistor FGT2 being spuriously programmed by a drain stress effect when the transistor is in the erased state. The spurious programming of the transistor FGT2 leads to the spurious programming of the transistor FGT1.
The voltage VD must not generally exceed 1 volt, i.e., a voltage Vcasc on the order of 2 volts. The data read at the input E3 depends on the programmed or erased state of the transistor FGT2, the latter being off in the erased state (data corresponding to a logic 1) or on in the programmed state (data corresponding by convention to a logic 0).
One principle of the present invention is to integrate a non-volatile register memory element into an EEPROM memory. The EEPROM comprising a memory array, a line decoder, a column decoder, and a read circuit. The memory array comprises normal bit lines and normal memory cells linked to the normal bit lines. Each normal memory cell comprises a floating-gate transistor comprising a tunnel window and a selection transistor.
However, such a memory element for a non-volatile register has various disadvantages. A first disadvantage of the memory element is that it requires control of the drain voltage VD of the floating-gate transistors, which requires providing the cascode transistors and the bias circuit delivering the voltage Vcasc. The bias circuit delivers the voltage Vcasc as soon as the supply voltage Vcc appears to enable the memory element to be rapidly read before the integrated circuit effectively starts up. Whether it is a simple voltage dividing bridge or a more complex bias circuit, such as a charge pump, the bias circuit has the disadvantage of consuming current. It also takes a certain amount of time to start up, such that the memory element cannot be read instantly when the supply voltage appears.
Another disadvantage of the memory element is that the reading thereof requires the application of the voltage Vcc to the selection input E0 of each memory point M11, M12 so that the selection transistor ST2 is on. A selection circuit for selecting the memory points M11, M12 must therefore be provided to transfer the data contained in the memory element to a dynamic register.
Another disadvantage of the memory element is that the reading thereof requires the application of the read voltage Vread to the gate control input E1. If the voltage Vread is zero as indicated above, a circuit for connecting the input E1 to ground should intervene when the data contained in the memory element is transferred to a dynamic register. As a result of all of these disadvantages, the memory element cannot easily be integrated into an EEPROM memory array.